@inproceedings{18c3c05f3fa24d2a878e68135c8243dc,
title = "A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting",
abstract = "This paper describes an interconnect technique for sub-threshold circuits to improve global wire delay and reduce the delay variation due to PVT fluctuations. By internally boosting the gate voltage of the driver transistors, operating region is shifted from sub-threshold region to super-threshold region enhancing performance and improving tolerance to PVT variations. A clock distribution network using the proposed drivers shows an 89% reduction in 3σ clock skew value. A 0.4V test chip has been fabricated in a 0.18μm 6-metal CMOS process to demonstrate the effectiveness of the proposed scheme. Measurement results show 2.6X faster switching speed and 2.4X less delay sensitivity under temperature variations.",
keywords = "Capacitive boosting, Clock skew, Global interconnect, Sub-threshold circuit, Variation tolerance",
author = "Jonggab Kil and Jie Gu and Kim, {Chris H.}",
year = "2006",
month = dec,
day = "1",
doi = "10.1145/1165573.1165590",
language = "English (US)",
isbn = "1595934626",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "67--72",
booktitle = "ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design",
note = "ISLPED'06 - 11th ACM/IEEE International Symposium on Low Power Electronics and Design ; Conference date: 04-10-2006 Through 06-10-2006",
}