A high-speed architecture for ADPCM codec

Naresh R. Shanbhag; Keshab K. Parhi

doi:10.1109/ISCAS.1992.230216

A high-speed architecture for ADPCM codec

Naresh R. Shanbhag, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of relaxed form of look-ahead. The hardware overhead is only the the pipelining latches and is independent of the number of quantizer levels, the predictor order and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with that of the serial one. Speech and image coding examples are presented to support the conclusions in this paper.

Original language	English (US)
Title of host publication	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1499-1502
Number of pages	4
ISBN (Electronic)	0780305930
DOIs	https://doi.org/10.1109/ISCAS.1992.230216
State	Published - 1992
Event	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 - San Diego, United States Duration: May 10 1992 → May 13 1992

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
ISSN (Print)	0271-4310

Conference

Conference	1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Country/Territory	United States
City	San Diego
Period	5/10/92 → 5/13/92

Bibliographical note

Publisher Copyright:
© 1992 IEEE.

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10.1109/ISCAS.1992.230216

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A high-speed architecture for ADPCM codec. / Shanbhag, Naresh R.; Parhi, Keshab K.
1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992. Institute of Electrical and Electronics Engineers Inc., 1992. p. 1499-1502 230216 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 3).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shanbhag, NR & Parhi, KK 1992, A high-speed architecture for ADPCM codec. in 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992., 230216, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3, Institute of Electrical and Electronics Engineers Inc., pp. 1499-1502, 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992, San Diego, United States, 5/10/92. https://doi.org/10.1109/ISCAS.1992.230216

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AB - A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of relaxed form of look-ahead. The hardware overhead is only the the pipelining latches and is independent of the number of quantizer levels, the predictor order and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with that of the serial one. Speech and image coding examples are presented to support the conclusions in this paper.

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ER -

A high-speed architecture for ADPCM codec

Abstract

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