Historically, buck converters have relied on high-Q inductors on the order of 1 to 100 μH to achieve a high efficiency. Unfortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efficiency converters. To mitigate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efficiency buck converter. The dramatic decrease in the inductance value is made possible by the unique bridge timing of the stacked design that causes magnetic coupling to boost the converter's efficiency by reducing the current ripple in each inductor. The magnetic coupling is realized by stacking the two inductors on top of one another, which not only lowers the required inductance, but also reduces the chip area consumed by the two inductors. The measured conversion efficiency for the prototype circuit, implemented in a 130-nm CMOS technology, shows more than a 15% efficiency improvement over a linear converter for low output voltages rising to a peak efficiency of 77.9% for a 0.9 V output. These efficiencies are comparable to converters implemented with higher Q inductors, validating that the proposed techniques enable high-efficiency converters to be realized with small on-chip inductors.
Bibliographical noteFunding Information:
Manuscript received July 7, 2007; revised October 17, 2007. This work was supported by Intel Corporation. Chip fabrication was provided by UMC. The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: harjani@umn. edu). Digital Object Identifier 10.1109/JSSC.2008.917321
Copyright 2008 Elsevier B.V., All rights reserved.
- Magnetic coupling
- Ripple cancellation
- Switch-mode voltage regulator
- Synchronous rectification