A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis

Kazuhito Ito, Keshab K Parhi

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

Original languageEnglish (US)
Pages (from-to)57-72
Number of pages16
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume16
Issue number1
StatePublished - Dec 1 1997

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