A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis

Kazuhito Ito, Keshab K Parhi

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

Original languageEnglish (US)
Pages (from-to)57-72
Number of pages16
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume16
Issue number1
StatePublished - Dec 1 1997

Fingerprint

Counting
Synthesis
Costs
Integer Linear Programming
Converter
Linear programming
Programming Model
Linear Model
Scheduling
Digital signal processing
Digit
Signal Processing
Architecture
Count
Schedule
Necessary

Cite this

@article{419e69fbd5cb498f80357b8e80826cde,
title = "A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis",
abstract = "In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8{\%} savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.",
author = "Kazuhito Ito and Parhi, {Keshab K}",
year = "1997",
month = "12",
day = "1",
language = "English (US)",
volume = "16",
pages = "57--72",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer New York",
number = "1",

}

TY - JOUR

T1 - A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis

AU - Ito, Kazuhito

AU - Parhi, Keshab K

PY - 1997/12/1

Y1 - 1997/12/1

N2 - In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

AB - In this paper we propose a generalized technique to count the required number of registers in a schedule which supports overlapped scheduling and can be applied to the case where a general digit-serial data format is used. This technique is integrated into an integer linear programming (ILP) model for time-constrained scheduling. In the ILP model, appropriate processors of certain data formats are chosen from a library of processors and data format converters are automatically inserted between processors of different data formats if necessary. Then the required number of registers for each data format is evaluated correctly by the proposed technique. Hence an optimal architecture for a given digital signal processing algorithm is synthesized where the cost of registers as well as the cost of processors and data format converters are minimized. It is shown that by including the cost of registers in the synthesis task as proposed in this paper leads to up to 12.8% savings in the total cost of the synthesized architecture when compared with synthesis performed without including the register cost in the total cost.

UR - http://www.scopus.com/inward/record.url?scp=0031142706&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031142706&partnerID=8YFLogxK

M3 - Article

VL - 16

SP - 57

EP - 72

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 1

ER -