A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning

Somnath Kundu, Muqing Liu, Richard Wong, Shi Jie Wen, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

Integrated voltage regulators with a wide output current/voltage dynamic range are required to support fast dynamic voltage and frequency scaling (DVFS). Low Dropout Regulators (LDOs) based on digital-intensive circuits have been gaining popularity [1]-[4] due to their compactness, process scalability, high immunity to process-voltage-temperature (PVT) variations and easy programmability for design optimization. Conventional digital LDOs utilizing a comparator and shift-registers [1] suffer from a slow response time during a large/fast change in load current (Iload). Higher sampling frequency (fS) improves the response time, but at the cost of increased power consumption and reduced loop stability. Multi-bit quantizers utilizing ADCs [2-4] can reduce the settling time, however, the presence of a high resolution ADC and the control logic increases the design complexity. Moreover, the ADC resolution limits the maximum fS. In order to overcome the trade-off between speed and power, adaptive sampling techniques were incorporated in [1], [4]. But the overhead of multiple VCOs operating simultaneously and a separate overshoot/droop detection circuitry [1], or an event-driven controller with 7b ADC [4], increase the complexity and power consumption. Furthermore, none of the previous designs incorporated active voltage positioning (AVP), a popular ripple-suppression technique, whereby the LDO output is set slightly above (in low-activity state) or below (in high-activity state) the reference voltage depending on the processor workload conditions [5].

Original languageEnglish (US)
Title of host publication2018 IEEE International Solid-State Circuits Conference, ISSCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages308-310
Number of pages3
ISBN (Electronic)9781509049394
DOIs
StatePublished - Mar 8 2018
Event65th IEEE International Solid-State Circuits Conference, ISSCC 2018 - San Francisco, United States
Duration: Feb 11 2018Feb 15 2018

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume61
ISSN (Print)0193-6530

Other

Other65th IEEE International Solid-State Circuits Conference, ISSCC 2018
Country/TerritoryUnited States
CitySan Francisco
Period2/11/182/15/18

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