A framework for block-based timing sensitivity analysis

Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitivities of the timing slacks to parameter variations. This additional slack information enables designers to examine paths that have large sensitivities to various parameters: such paths are not robust, even though they may have large nominal slacks and may hence be ignored in traditional timing analysis. We present a framework for block-based timing analysis, where the parameters are specified as ranges - rather than statistical distributions which are hard to know in practice. We show that our approach - which scales well with the number of processors - is accurate at all values of the parameters within the specified bounds, and not just at the worstcase corner. This allows the designers to quantify the robustness of the design at any design point. We validate our approach on circuit blocks extracted from a commercial 45nm microprocessor.

Original languageEnglish (US)
Title of host publicationProceedings of the 45th Design Automation Conference, DAC
Pages688-693
Number of pages6
DOIs
StatePublished - Sep 17 2008
Event45th Design Automation Conference, DAC - Anaheim, CA, United States
Duration: Jun 8 2008Jun 13 2008

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other45th Design Automation Conference, DAC
CountryUnited States
CityAnaheim, CA
Period6/8/086/13/08

Keywords

  • Arrival times
  • Pruning
  • Reordering
  • Slacks
  • Variations

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