A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations

Keyphrases

• SRAM Cache 100%
• Low Leakage 100%
• Forward Body Biasing 100%
• Ultra-high 66%
• SRAM Cell 66%
• Caching 33%
• Circuit Architecture 33%
• Energy Overhead 33%
• Leakage Power 33%
• Bitline 33%
• Threshold Voltage 33%
• Cache Memory 33%
• Leakage Reduction 33%
• Nanoscale Regime 33%
• Doping Profile 33%
• Wake-up 33%
• Latency Overhead 33%
• Fast Operation 33%
• Biasing Scheme 33%
• Leakage Mechanism 33%
• Leakage Power Reduction 33%
• Active Leakage Control 33%
• Halo Doping 33%
• Cache Access Pattern 33%
• Combination Device 33%
• Architectural Level 33%

Computer Science

• Level Technique 100%
• Bitline 100%
• Architecture Level 100%
• Access Pattern 100%
• Cache Memory 100%
• Device Threshold Voltage 100%

Engineering

• Super High 100%
• Nanometre 50%
• Energy Engineering 50%
• Device Threshold Voltage 50%