Negative bias temperature instability (NBTI) in PMOS transistors has become a serious reliability concern in present-day digital circuit design. With continued technology scaling, and reducing oxide thickness, it has become imperative to accurately determine its effects on temporal circuit degradation, and thereby ensure reliable operation for a finite period of time. A reactiondiffusion (RD)-based framework is developed for determining the number of interface traps as a function of time, for both the dc (static NBTI) and the ac (dynamic NBTI) stress cases. The effects of finite oxide thickness, and the influence of trap generation and annealing in polysilicon, are incorporated. The model provides a good fit with experimental data and also provides a satisfying explanation for most of the physical effects associated with the dynamics of NBTI. A generalized framework for estimating the impact of NBTI-induced temporal degradation in present-day digital circuits, is also discussed.
|Original language||English (US)|
|Number of pages||20|
|Journal||IEEE Transactions on Device and Materials Reliability|
|State||Published - Dec 2009|
Bibliographical noteFunding Information:
Manuscript received December 25, 2008; revised April 4, 2009. First published July 31, 2009; current version published December 3, 2009. This work was supported in part by the National Science Foundation under Award CCF-0541367 and in part by the Semiconductor Research Corporation under Contract 2007-TJ-1572.
- Frequency independence
- Negative bias temperature instability (NBTI)
- Oxide thickness
- Reaction-diffusion (R-D) model