A Fast VLSI Adder Architecture

H. R. Srinivas, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

44 Scopus citations


In this paper we present an architecture for performing fixed-point, high-speed, two’s-complement, bit-parallel addition by using the carry-free property of redundant arithmetic and a fast parallel redundant-to-binary conversion scheme. In this architecture, the internal numbers are represented in radix-2 redundant digit form and the inputs and the output of the adder are represented in two’s-complement binary form. The adder operands are added first in a radix-2 redundant adder to produce the result in radix-2 digit (-1, 0, 1) form. This result is then converted to two’s-complement binary form by using the proposed fast parallel conversion scheme. The high-speed conversion for long words is achieved through the use of a novel sign-select operation. This proposed adder is referred to as the sign-select conversion adder and is faster than all previous high-speed two’s-complement binary adders for large word lengths (although it requires larger area). For word lengths between 16 and 64, the proposed design is 20-28% faster than the fastest known binary lookahead adder. The implementation is highly regular with repeated modules and is very well suited for VLSI implementation.

Original languageEnglish (US)
Pages (from-to)761-767
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - May 1992

Bibliographical note

Funding Information:
Manuscript received October 9. 1991; January 3, 1992. This work was supported by the Office of Naval Research under Contract N00014-J-91-1008. The authors are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455. IEEE Log Number 9107340.


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