A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS

Satwik Patnaik; Narasimha Lanka; Ramesh Harjani

doi:10.1109/ISSCC.2009.4977522

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS

Satwik Patnaik, Narasimha Lanka, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Original language	English (US)
Title of host publication	2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	490-492
Number of pages	3
ISBN (Print)	1424434580, 9781424434589
DOIs	https://doi.org/10.1109/ISSCC.2009.4977522
State	Published - 2009
Event	2009 IEEE International Solid-State Circuits Conference ISSCC 2009 - San Francisco, CA, United States Duration: Feb 8 2009 → Feb 12 2009

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	2009 IEEE International Solid-State Circuits Conference ISSCC 2009
Country/Territory	United States
City	San Francisco, CA
Period	2/8/09 → 2/12/09

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10.1109/ISSCC.2009.4977522

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Patnaik, S., Lanka, N., & Harjani, R. (2009). A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009 (pp. 490-492). Article 4977522 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2009.4977522

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS. / Patnaik, Satwik; Lanka, Narasimha; Harjani, Ramesh.
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. Institute of Electrical and Electronics Engineers Inc., 2009. p. 490-492 4977522 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Patnaik, S, Lanka, N & Harjani, R 2009, A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS. in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009., 4977522, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 490-492, 2009 IEEE International Solid-State Circuits Conference ISSCC 2009, San Francisco, CA, United States, 2/8/09. https://doi.org/10.1109/ISSCC.2009.4977522

Patnaik S, Lanka N, Harjani R. A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. Institute of Electrical and Electronics Engineers Inc. 2009. p. 490-492. 4977522. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2009.4977522

Patnaik, Satwik ; Lanka, Narasimha ; Harjani, Ramesh. / A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS. 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. Institute of Electrical and Electronics Engineers Inc., 2009. pp. 490-492 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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A dual-mode architecture for a phased-array receiver based on injection locking in 0.13μm CMOS

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