Analog IC placement is typically a manual process that requires strong experience and trial-and-error iterations as it produces a large impact to circuit performance in a complicated manner. Although automatic analog placement has been studied for decades, existing methods are inadequate for achieving performance comparable with manual designs. In this work, a customized graph neural network model is developed for predicting the impact of placement on circuit performance. Knowledge obtained by such a model can be transferred among different topologies of the same circuit type. Simulation results show that the proposed model is superior to a recent CNN-based work in terms of both accuracy and knowledge transfer. It also outperforms a plug-in use of graph attention network. The proposed model is further applied in analog IC placement and achieves performance similar to manual designs.
|Original language||English (US)|
|Journal||IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD|
|State||Published - Nov 2 2020|
|Event||39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020 - Virtual, San Diego, United States|
Duration: Nov 2 2020 → Nov 5 2020
Bibliographical noteFunding Information:
This work is supported by the DARPA ERI IDEA program. We thank Prof. Shuiwang Ji of Texas A&M University for helpful discussions.
© 2020 Association on Computer Machinery.