A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

Keyphrases

• Low Voltage 100%
• D Flip-flop 100%
• Glitch-free 100%
• Flip-flop Circuit 100%
• Supply Voltage 50%
• Superior Performance 25%
• CMOS Technology 25%
• Power Consumption 25%
• Low Power Consumption 25%
• Large Reduction 25%
• Design Objectives 25%
• Low-voltage Operation 25%
• HSPICE 25%
• Dynamic Power Consumption 25%
• Pipelined multiplier 25%
• Multiplier Design 25%
• Free Operation 25%

Engineering

• Flip Flop Circuits 100%
• Supply Voltage 100%
• Electric Power Utilization 40%
• Design Objective 20%
• Low Power Consumption 20%