A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V²_dd, decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.