Modern wireless communication systems require power amplifiers with high efficiency and high linearity. CMOS is the technology of choice for complete systems on a chip due to its lower costs and high integration levels. However, in the past it has always been difficult to integrate high efficiency power amplifiers in CMOS. In this paper we present a new class of operation (parallel A&B) for power amplifiers that improves both their dynamic range and power efficiency. A prototype design of the new amplifier was fabricated in a 0.18μn CMOS technology. The measurement results show over 44% PAE and +22 dBm output power. In comparison to a normal class A amplifier, this new design increases the P1dB by over 3 dB and yet reduces DC power consumption by up to 50% in the linear operation range.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Dec 1 2004|
|Event||Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC - Orlando, FL, United States|
Duration: Oct 3 2004 → Oct 6 2004