Analog integrated circuit design is highly complex and its automation is a long-standing challenge. We present a reinforcement learning approach to automatic transistor sizing, a key step in determining analog circuit performance. A circuit attention network technique is developed to capture the impact of transistor sizing on circuit performance in an actor-critic learning framework. Our approach also includes a stochastic technique for addressing layout effect, another important factor affecting performance. Compared to Bayesian optimization (BO) and Graph Convolutional Network-based reinforcement learning (GCN-RL), two state-of-the-art methods, the proposed approach significantly improves robustness against layout uncertainty while achieving better post-layout performance. BO and GCN-RL can be enhanced with our stochastic technique to reach solution quality similar to ours, but still suffer from a much slower convergence rate. Moreover, the knowledge transfer in our approach is more effective than that in GCN-RL.
|Original language||English (US)|
|Title of host publication||2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD, MLCAD 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Aug 30 2021|
|Event||3rd ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2021 - Raleigh, United States|
Duration: Aug 30 2021 → Sep 3 2021
|Name||2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD)|
|Conference||3rd ACM/IEEE Workshop on Machine Learning for CAD, MLCAD 2021|
|Period||8/30/21 → 9/3/21|
Bibliographical noteFunding Information:
ACKNOWLEDGEMENT This work is supported by the DARPA ERI IDEA program.
© 2021 IEEE.