A chip-level electrostatic discharge simulation strategy

Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

This paper presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node V DD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

Original languageEnglish (US)
Title of host publicationICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages315-318
Number of pages4
DOIs
StatePublished - Dec 1 2004
EventICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 7 2004Nov 11 2004

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)1092-3152

Other

OtherICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
CountryUnited States
CitySan Jose, CA
Period11/7/0411/11/04

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