A C-Testable Carry-Free Divider

H. R. Srinivas, Bapiraju Vinnakota, Keshab K Parhi

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W2) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two’s-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+ 10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal.

Original languageEnglish (US)
Pages (from-to)472-488
Number of pages17
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume2
Issue number4
DOIs
StatePublished - Jan 1 1994

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A C-Testable Carry-Free Divider. / Srinivas, H. R.; Vinnakota, Bapiraju; Parhi, Keshab K.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 2, No. 4, 01.01.1994, p. 472-488.

Research output: Contribution to journalArticle

Srinivas, H. R. ; Vinnakota, Bapiraju ; Parhi, Keshab K. / A C-Testable Carry-Free Divider. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1994 ; Vol. 2, No. 4. pp. 472-488.
@article{a48b352b092e40139b2cde6d7db7b523,
title = "A C-Testable Carry-Free Divider",
abstract = "In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W2) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two’s-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+ 10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal.",
author = "Srinivas, {H. R.} and Bapiraju Vinnakota and Parhi, {Keshab K}",
year = "1994",
month = "1",
day = "1",
doi = "10.1109/92.335015",
language = "English (US)",
volume = "2",
pages = "472--488",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "4",

}

TY - JOUR

T1 - A C-Testable Carry-Free Divider

AU - Srinivas, H. R.

AU - Vinnakota, Bapiraju

AU - Parhi, Keshab K

PY - 1994/1/1

Y1 - 1994/1/1

N2 - In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W2) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two’s-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+ 10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal.

AB - In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W2) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two’s-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+ 10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal.

UR - http://www.scopus.com/inward/record.url?scp=0028712726&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028712726&partnerID=8YFLogxK

U2 - 10.1109/92.335015

DO - 10.1109/92.335015

M3 - Article

AN - SCOPUS:0028712726

VL - 2

SP - 472

EP - 488

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 4

ER -