A C-Testable Carry-Free Divider

H. R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


In this paper, the design of a C-testable, high-performance carry-free array divider is presented. A radix-2 redundant number based carry-free divider is considered and is modified to make it C-testable, i.e., it can be exhaustively tested using a constant number of test vectors irrespective of its word-length. Previous C-testable designs considered dividers which used carry-propagate adders/subtractors. These dividers are slow because of their O(W2) computation time (where W is the word-length of the divider). High-performance carry-free dividers use carry-free redundant arithmetic adders/subtractors. Due to this feature, they have O(W) computation time. The on-the-fly converter used by carry-free dividers to convert the redundant quotient to two’s-complement form is shown to be not C-testable. It is modified to be linear-testable (in word-length) instead of exponential time required for exhaustive testing of all possible combinations at its inputs. We conclude that the number of test vectors needed is 99 for C-testing of the divider array and (3W+ 10) for linear testing of the converter. The hardware overhead required to make the divider C-testable and the on-the-fly converter linear testable is also shown to be nominal.

Original languageEnglish (US)
Pages (from-to)472-488
Number of pages17
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
StatePublished - Dec 1994

Bibliographical note

Funding Information:
Manuscript received July 26, 1993; revised February 2, 1994 and June 20, 1994. This work was supported by the Office of Naval Research under Contract NOO014-J-91-1 008. The authors are with the Department of Electrical Engineering, University of Minnesota, Minneapolis, MN 55455 USA. IEEE Log Number 9405513.


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