A bit-by-bit re-writable eflash in a generic 65 nm logic process for moderate-density nonvolatile memory applications

Seung Hwan Song, Ki Chul Chun, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

Embedded nonvolatile memory (eNVM) is considered to be a critical building block in future system-on-chip and microprocessor systems. Various eNVM technologies have been explored for high-density applications including dual-poly embedded flash (eflash), FeRAM, STT-MRAM, and RRAM. On the other end of the spectrum, logic-compatible eNVM such as e-fuse, anti-fuse, and single-poly eflash memories have been considered for moderate-density low-cost applications. In particular, single-poly eflash memory has been gaining momentum as it can be implemented in a generic logic process while supporting multiple program-erase cycles. One key challenge for single-poly eflash is enabling bit-by-bit re-write operation without a boosted bitline voltage as this could cause disturbance issues in the unselected wordlines. In this work, we present details of a bit-by-bit re-writable eflash memory implemented in a generic 65 nm logic process which addresses this key challenge. The proposed 6 T eflash memory cell can improve the overall cell endurance by eliminating redundant program/erase cycles while preventing disturbance issues in the unselected wordlines. We also provide details of special high voltage circuits such as a voltage-doubler based charge pump circuit and a multistory high-voltage switch, for generating a reliable high-voltage output without causing damage to the standard logic transistors.

Original languageEnglish (US)
Article number6799274
Pages (from-to)1861-1871
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number8
DOIs
StatePublished - Aug 2014

Keywords

  • Charge pump
  • embedded nonvolatile memory (eNVM)
  • negative high-voltage switch
  • nonvolatile memory (NVM)
  • single-poly embedded flash memory

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