A balanced approach to high-level verification: Performance trade-offs in verifying large-scale multiprocessors

Keyphrases

• Multiprocessor 100%
• Balanced Approach 100%
• Performance Tradeoff 100%
• Raven 100%
• High-level Verification 100%
• Verification Performance 100%
• Performance Analysis 50%
• Verilog 50%
• Shared-memory multiprocessors 50%
• Verification Process 50%
• Architectural Features 50%
• Model Checker 50%
• Simulation Techniques 50%
• Single Processor 50%
• Performance Implications 50%
• Single Node 50%
• Levels of Abstraction 50%
• Discrete Event 50%
• Test Vector 50%
• Integration Level 50%
• Cache Coherence Protocol 50%
• Verification Framework 50%
• Memory Consistency Models 50%
• Logic Simulation 50%
• Event Logic 50%
• Complexity Level 50%
• Conventional Simulator 50%

Computer Science

• Level Verification 100%
• multi-processor 100%
• Performance Trade 100%
• Shared Memory Multiprocessor 50%
• Simulation Mode 50%
• Model Checking 50%
• Single Processor 50%
• Verilog 50%
• Performance Implication 50%
• Memory Consistency 50%
• Logic Simulation 50%
• Primitive Interface 50%
• model checker 50%
• Performance Analysis 50%
• Application Specific Integrated Circuit 50%
• Cache Coherence 50%
• Verification Process 50%