A balanced approach to high-level verification: Performance trade-offs in verifying large-scale multiprocessors

D. Abts, M. Roberts, D. J. Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A single node of a modern scalable multiprocessor consists of several ASICs comprising tens of millions of gates. This level of integration and complexity imposes an enormous onus on the verification process. A variety of tools, ranging from discrete-event logic simulation to formal model checking, can be used to attack this problem. Unfortunately, conventional simulation techniques, with their primitive interface to the hardware (i.e. test vectors), are inadequate tools for reasoning about the correctness of complex architectural features, such as cache coherence protocols and memory consistency models. Similarly, model checkers offer very limited utility on such large designs. We have previously proposed a novel verification framework, called Raven, that addresses many of these challenges. In this paper we examine the performance implications of verifying systems at higher levels of abstraction. A detailed performance analysis is conducted to compare this higher-level approach against an equivalent Verilog test bench. We establish lower and upper bounds on the performance of the Raven environment executing on a single-processor on a set of distributed processors, and on a shared-memory multiprocessor.

Original languageEnglish (US)
Title of host publicationProceedings - 2000 International Conference on Parallel Processing, ICPP 2000
EditorsDavid J. Lilja
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages505-510
Number of pages6
ISBN (Electronic)0769507689
DOIs
StatePublished - Jan 1 2000
EventInternational Conference on Parallel Processing, ICPP 2000 - Toronto, Canada
Duration: Aug 21 2000Aug 24 2000

Publication series

NameProceedings of the International Conference on Parallel Processing
Volume2000-January
ISSN (Print)0190-3918

Other

OtherInternational Conference on Parallel Processing, ICPP 2000
CountryCanada
CityToronto
Period8/21/008/24/00

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Keywords

  • Application specific integrated circuits
  • Coherence
  • Hardware design languages
  • Large-scale systems
  • Libraries
  • Logic design
  • Logic programming
  • Multiprocessing systems
  • Protocols
  • Testing

Cite this

Abts, D., Roberts, M., & Lilja, D. J. (2000). A balanced approach to high-level verification: Performance trade-offs in verifying large-scale multiprocessors. In D. J. Lilja (Ed.), Proceedings - 2000 International Conference on Parallel Processing, ICPP 2000 (pp. 505-510). [876167] (Proceedings of the International Conference on Parallel Processing; Vol. 2000-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICPP.2000.876167