A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter

K. Nair; R. Harjani

A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter

K. Nair, R. Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

33 Scopus citations

Abstract

A 96dB SFDR 50MS/S pipeline A/D converter has been designed in a 0.25μm CMOS process. An improved sample-and-hold and SD-CGC digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49dB to 75dB and the SFDR increases from 62dB to 96dB using the technique.

Original language	English (US)
Title of host publication	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Editors	L.C. Fujino, M. Amiri, A. Grabel, D. Jaeger, K.C. Smith
Volume	47
State	Published - 2003
Event	Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States Duration: Feb 15 2003 → Feb 19 2003

Other

Other	Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference
Country/Territory	United States
City	San Francisco, CA.
Period	2/15/03 → 2/19/03

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Nair, K & Harjani, R 2003, A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter. in LC Fujino, M Amiri, A Grabel, D Jaeger & KC Smith (eds), Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 47, Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, San Francisco, CA., United States, 2/15/03.

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title = "A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter",

abstract = "A 96dB SFDR 50MS/S pipeline A/D converter has been designed in a 0.25μm CMOS process. An improved sample-and-hold and SD-CGC digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49dB to 75dB and the SFDR increases from 62dB to 96dB using the technique.",

author = "K. Nair and R. Harjani",

year = "2003",

language = "English (US)",

volume = "47",

editor = "L.C. Fujino and M. Amiri and A. Grabel and D. Jaeger and K.C. Smith",

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note = "Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference ; Conference date: 15-02-2003 Through 19-02-2003",

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AU - Nair, K.

AU - Harjani, R.

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AB - A 96dB SFDR 50MS/S pipeline A/D converter has been designed in a 0.25μm CMOS process. An improved sample-and-hold and SD-CGC digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49dB to 75dB and the SFDR increases from 62dB to 96dB using the technique.

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M3 - Conference contribution

AN - SCOPUS:2442637791

VL - 47

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

A2 - Fujino, L.C.

A2 - Amiri, M.

A2 - Grabel, A.

A2 - Jaeger, D.

A2 - Smith, K.C.

T2 - Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference

Y2 - 15 February 2003 through 19 February 2003

ER -

A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter

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