A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter

K. Nair, R. Harjani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

32 Scopus citations

Abstract

A 96dB SFDR 50MS/S pipeline A/D converter has been designed in a 0.25μm CMOS process. An improved sample-and-hold and SD-CGC digital calibration are used to increase linearity. Prototype measurements show that the SNDR increases from 49dB to 75dB and the SFDR increases from 62dB to 96dB using the technique.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
EditorsL.C. Fujino, M. Amiri, A. Grabel, D. Jaeger, K.C. Smith
Volume47
StatePublished - 2003
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: Feb 15 2003Feb 19 2003

Other

OtherDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference
CountryUnited States
CitySan Francisco, CA.
Period2/15/032/19/03

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Nair, K., & Harjani, R. (2003). A 96dB SFDR 50MS/s digitally enhanced CMOS pipeline A/D converter. In L. C. Fujino, M. Amiri, A. Grabel, D. Jaeger, & K. C. Smith (Eds.), Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 47)