Abstract
Efficient power management for RF power amplifiers (PAs) is emerging as a critical requirement for the development and adoption of next-generation wireless communication systems. To achieve higher transmitter efficiency, envelope tracking (ET) using supply modulators (SM) is widely used in today's systems. However, the demands for high bandwidth, complex modulation and multiple access schemes in 5G and upcoming 6G systems have exposed serious limitations of analog ET (AET) that get worse in high-power high-voltage applications, e.g., base-station transmitters. As a promising alternative to AET, digital envelope tracking (DET) has proven its advantages and capabilities to support various signal bandwidths and power profiles [1]-[8]. DET architectures in Figure 9.3.1 achieve higher efficiency by separating the voltage generation (VG) stage and tracker (TR) stage, in which the former aimed for relatively slow but efficient generations of multiple voltage levels and the latter for fast voltage tracking.
| Original language | English (US) |
|---|---|
| Title of host publication | 2025 IEEE International Solid-State Circuits Conference, ISSCC 2025 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798331541019 |
| DOIs | |
| State | Published - 2025 |
| Event | 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 - San Francisco, United States Duration: Feb 16 2025 → Feb 20 2025 |
Publication series
| Name | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
|---|---|
| ISSN (Print) | 0193-6530 |
Conference
| Conference | 72nd IEEE International Solid-State Circuits Conference, ISSCC 2025 |
|---|---|
| Country/Territory | United States |
| City | San Francisco |
| Period | 2/16/25 → 2/20/25 |
Bibliographical note
Publisher Copyright:© 2025 IEEE.
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