A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies

6T SRAMs have been the embedded memory of choice for modern microprocessors due to their logic compatibility, high speed, and refresh-free operation. The relatively large cell size and conflicting requirements for read and write at low operating voltages make aggressive scaling of 6T SRAMs challenging in sub-22nm. Recently, 1T1C embedded DRAMs (eDRAMs) have replaced SRAMs in several server applications reducing the cache area and improving performance [1]. Difficulties in scaling the trench capacitor and the additional process steps involved in manufacturing the thick oxide access devices are currently limiting the wide spread adoption of 1T1C technology. Gain cells have features such as decoupled read and write paths, a nondestructive read, and a 2X higher bit-cell density than a 6T SRAM, making them a strong contender for future embedded memories [2-4]. However, the boosted supplies needed for robust operation necessitates thick oxide devices to prevent gate reliability issues in gain cells. Although this would lead to a larger bit-cell size and decreased macro performance, these limitations have been overlooked in the past. In this paper, we present the following circuit techniques for realizing a truly logic compatible (i.e. thin oxide only implementation) gain cell eDRAM with no boosted supplies; (i) a 2T1C gain cell featuring a beneficial couple-up read and a preferential couple-down write, (ii) a single-ended 7T SRAM to repair weak gain cells, and (iii) a storage voltage monitor capable of tracking PVT and cell retention time for adaptive refresh control. The 64kb test macro in Fig. 28.10.1 achieves a random cycle frequency of 700MHz and a retention time of 500μsec.