A neuromorphic core utilizing logic-compatible embedded flash technology for storing multi-level synaptic weights is demonstrated in a 65nm standard CMOS process. A carefully-designed program-verify sequence along with a bitline voltage regulation scheme allows the individual cell currents to be programmed precisely. This makes it possible to enable a large number of rows in parallel without impacting the current summation accuracy. Furthermore, eflash based synapses are non-volatile and hence consumes zero standby power and supports instant on/off operation. Our design stores excitatory and inhibitory weights in adjacent bitlines whose voltage levels are regulated for accurate current programming and measurement. Output spikes are generated by comparing the excitatory and inhibitory bitline currents. Our logic-compatible eflash-based spiking neuromorphic core achieves a 91.8% handwritten digit recognition accuracy which is close to the accuracy of the software model with the same number of weight levels. The maximum throughput of the core is 1.28G pixels/s and the average power consumption of a single neuron circuit is 15.9μ W.
|Original language||English (US)|
|Title of host publication||2018 IEEE International Electron Devices Meeting, IEDM 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Jan 16 2019|
|Event||64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States|
Duration: Dec 1 2018 → Dec 5 2018
|Name||Technical Digest - International Electron Devices Meeting, IEDM|
|Conference||64th Annual IEEE International Electron Devices Meeting, IEDM 2018|
|Period||12/1/18 → 12/5/18|
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