A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology

M. Kim, J. Kim, C. Park, L. Everson, H. Kim, S. Song, S. Lee, C. H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A neuromorphic core utilizing logic-compatible embedded flash technology for storing multi-level synaptic weights is demonstrated in a 65nm standard CMOS process. A carefully-designed program-verify sequence along with a bitline voltage regulation scheme allows the individual cell currents to be programmed precisely. This makes it possible to enable a large number of rows in parallel without impacting the current summation accuracy. Furthermore, eflash based synapses are non-volatile and hence consumes zero standby power and supports instant on/off operation. Our design stores excitatory and inhibitory weights in adjacent bitlines whose voltage levels are regulated for accurate current programming and measurement. Output spikes are generated by comparing the excitatory and inhibitory bitline currents. Our logic-compatible eflash-based spiking neuromorphic core achieves a 91.8% handwritten digit recognition accuracy which is close to the accuracy of the software model with the same number of weight levels. The maximum throughput of the core is 1.28G pixels/s and the average power consumption of a single neuron circuit is 15.9μ W.

Original languageEnglish (US)
Title of host publication2018 IEEE International Electron Devices Meeting, IEDM 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15.4.1-15.4.4
ISBN (Electronic)9781728119878
DOIs
StatePublished - Jan 16 2019
Event64th Annual IEEE International Electron Devices Meeting, IEDM 2018 - San Francisco, United States
Duration: Dec 1 2018Dec 5 2018

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2018-December
ISSN (Print)0163-1918

Conference

Conference64th Annual IEEE International Electron Devices Meeting, IEDM 2018
CountryUnited States
CitySan Francisco
Period12/1/1812/5/18

Fingerprint

synapses
Flash memory
Voltage control
Neurons
logic
flash
Electric power utilization
Pixels
Throughput
Networks (circuits)
Electric potential
spiking
digits
electric potential
programming
neurons
spikes
CMOS
pixels
computer programs

Cite this

Kim, M., Kim, J., Park, C., Everson, L., Kim, H., Song, S., ... Kim, C. H. (2019). A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology. In 2018 IEEE International Electron Devices Meeting, IEDM 2018 (pp. 15.4.1-15.4.4). [8614599] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2018.8614599

A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology. / Kim, M.; Kim, J.; Park, C.; Everson, L.; Kim, H.; Song, S.; Lee, S.; Kim, C. H.

2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 15.4.1-15.4.4 8614599 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2018-December).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kim, M, Kim, J, Park, C, Everson, L, Kim, H, Song, S, Lee, S & Kim, CH 2019, A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology. in 2018 IEEE International Electron Devices Meeting, IEDM 2018., 8614599, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2018-December, Institute of Electrical and Electronics Engineers Inc., pp. 15.4.1-15.4.4, 64th Annual IEEE International Electron Devices Meeting, IEDM 2018, San Francisco, United States, 12/1/18. https://doi.org/10.1109/IEDM.2018.8614599
Kim M, Kim J, Park C, Everson L, Kim H, Song S et al. A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology. In 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 15.4.1-15.4.4. 8614599. (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2018.8614599
Kim, M. ; Kim, J. ; Park, C. ; Everson, L. ; Kim, H. ; Song, S. ; Lee, S. ; Kim, C. H. / A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology. 2018 IEEE International Electron Devices Meeting, IEDM 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 15.4.1-15.4.4 (Technical Digest - International Electron Devices Meeting, IEDM).
@inproceedings{3c99153be34f4158bc98df146c9e3d4f,
title = "A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology",
abstract = "A neuromorphic core utilizing logic-compatible embedded flash technology for storing multi-level synaptic weights is demonstrated in a 65nm standard CMOS process. A carefully-designed program-verify sequence along with a bitline voltage regulation scheme allows the individual cell currents to be programmed precisely. This makes it possible to enable a large number of rows in parallel without impacting the current summation accuracy. Furthermore, eflash based synapses are non-volatile and hence consumes zero standby power and supports instant on/off operation. Our design stores excitatory and inhibitory weights in adjacent bitlines whose voltage levels are regulated for accurate current programming and measurement. Output spikes are generated by comparing the excitatory and inhibitory bitline currents. Our logic-compatible eflash-based spiking neuromorphic core achieves a 91.8{\%} handwritten digit recognition accuracy which is close to the accuracy of the software model with the same number of weight levels. The maximum throughput of the core is 1.28G pixels/s and the average power consumption of a single neuron circuit is 15.9μ W.",
author = "M. Kim and J. Kim and C. Park and L. Everson and H. Kim and S. Song and S. Lee and Kim, {C. H.}",
year = "2019",
month = "1",
day = "16",
doi = "10.1109/IEDM.2018.8614599",
language = "English (US)",
series = "Technical Digest - International Electron Devices Meeting, IEDM",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "15.4.1--15.4.4",
booktitle = "2018 IEEE International Electron Devices Meeting, IEDM 2018",

}

TY - GEN

T1 - A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology

AU - Kim, M.

AU - Kim, J.

AU - Park, C.

AU - Everson, L.

AU - Kim, H.

AU - Song, S.

AU - Lee, S.

AU - Kim, C. H.

PY - 2019/1/16

Y1 - 2019/1/16

N2 - A neuromorphic core utilizing logic-compatible embedded flash technology for storing multi-level synaptic weights is demonstrated in a 65nm standard CMOS process. A carefully-designed program-verify sequence along with a bitline voltage regulation scheme allows the individual cell currents to be programmed precisely. This makes it possible to enable a large number of rows in parallel without impacting the current summation accuracy. Furthermore, eflash based synapses are non-volatile and hence consumes zero standby power and supports instant on/off operation. Our design stores excitatory and inhibitory weights in adjacent bitlines whose voltage levels are regulated for accurate current programming and measurement. Output spikes are generated by comparing the excitatory and inhibitory bitline currents. Our logic-compatible eflash-based spiking neuromorphic core achieves a 91.8% handwritten digit recognition accuracy which is close to the accuracy of the software model with the same number of weight levels. The maximum throughput of the core is 1.28G pixels/s and the average power consumption of a single neuron circuit is 15.9μ W.

AB - A neuromorphic core utilizing logic-compatible embedded flash technology for storing multi-level synaptic weights is demonstrated in a 65nm standard CMOS process. A carefully-designed program-verify sequence along with a bitline voltage regulation scheme allows the individual cell currents to be programmed precisely. This makes it possible to enable a large number of rows in parallel without impacting the current summation accuracy. Furthermore, eflash based synapses are non-volatile and hence consumes zero standby power and supports instant on/off operation. Our design stores excitatory and inhibitory weights in adjacent bitlines whose voltage levels are regulated for accurate current programming and measurement. Output spikes are generated by comparing the excitatory and inhibitory bitline currents. Our logic-compatible eflash-based spiking neuromorphic core achieves a 91.8% handwritten digit recognition accuracy which is close to the accuracy of the software model with the same number of weight levels. The maximum throughput of the core is 1.28G pixels/s and the average power consumption of a single neuron circuit is 15.9μ W.

UR - http://www.scopus.com/inward/record.url?scp=85061768963&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85061768963&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2018.8614599

DO - 10.1109/IEDM.2018.8614599

M3 - Conference contribution

AN - SCOPUS:85061768963

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 15.4.1-15.4.4

BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -