A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer

Po Wei Chiu, Somnath Kundu, Qianying Tang, Chris H. Kim

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

A digital-intensive on-chip serial link achieving a 10 Gb/s data rate over a 10-mm interconnect was demonstrated in a 65-nm GP process. A three-tap half-rate feed-forward equalizer was implemented for signal pre-emphasis in the transmitted block. On the receiver (RX) side, a two-tap half-rate time-based decision feedback equalizer was employed to cancel out inter-symbol interference noise. A 215-1 pseudorandom binary sequence generator and an in situ bit error rate (BER) monitor were designed for bit stream generation and convenient eye-diagram measurements. The measured energy efficiency of the transmitter and RX was 31.9 and 45.3 fJ/b/mm, respectively, for a data rate of 10 Gb/s. A BER less than 10-12 was verified for an eye width of 0.43 unit interval.

Original languageEnglish (US)
Pages (from-to)1203-1213
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume53
Issue number4
DOIs
StatePublished - Apr 2018

Keywords

  • Digital intensive
  • eye diagram
  • feed-forward equalizer (FFE)
  • in situ bit error rate (BER) monitor
  • pseudorandom binary sequence (PRBS)
  • time-based decision feedback equalizer (TB-DFE)

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