A digital-intensive on-chip serial link achieving a 10 Gb/s data rate over a 10-mm interconnect was demonstrated in a 65-nm GP process. A three-tap half-rate feed-forward equalizer was implemented for signal pre-emphasis in the transmitted block. On the receiver (RX) side, a two-tap half-rate time-based decision feedback equalizer was employed to cancel out inter-symbol interference noise. A 215-1 pseudorandom binary sequence generator and an in situ bit error rate (BER) monitor were designed for bit stream generation and convenient eye-diagram measurements. The measured energy efficiency of the transmitter and RX was 31.9 and 45.3 fJ/b/mm, respectively, for a data rate of 10 Gb/s. A BER less than 10-12 was verified for an eye width of 0.43 unit interval.
Bibliographical noteFunding Information:
Manuscript received August 5, 2017; revised October 10, 2017 and November 5, 2017; accepted November 7, 2017. Date of publication December 6, 2017; date of current version March 23, 2018. This paper was approved by Guest Editor Ken Chang. This work was supported in part by the National Science Foundation Award under Grant CCF-1255937 and in part by the Semiconductor Research Corporation under Grant 2013-HJ-2409. (Corresponding author: Po-Wei Chiu.) P.-W. Chiu and C. H. Kim are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: firstname.lastname@example.org).
© 2012 IEEE.
- Digital intensive
- eye diagram
- feed-forward equalizer (FFE)
- in situ bit error rate (BER) monitor
- pseudorandom binary sequence (PRBS)
- time-based decision feedback equalizer (TB-DFE)