A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os

Taehyoun Oh; Ramesh Harjani

doi:10.1109/CICC.2010.5617599

A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os

Taehyoun Oh, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

We describe a multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture, particularly applicable to single-ended I/O. The MIMO architecture efficiently cancels crosstalk and improves jitter and eye-opening at the same time. A continuous-time prototype design was fabricated using a 130nm CMOS process and occupies 0.03mm² of die area. The XTC equalizer performance has been verified for a variety of FR4 channel spacings and data rates. Measured eye diagrams show that the jitter_pp reduces by 67%UI and the vertical eye opening increases by 58.2% at 5Gb/s. The prototype MIMO-XTC circuit consumes 2.8 mW/Gbps/lane which is roughly 2 times lower than other XTC schemes.

Original language	English (US)
Title of host publication	IEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs	https://doi.org/10.1109/CICC.2010.5617599
State	Published - 2010
Event	32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States Duration: Sep 19 2010 → Sep 22 2010

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
Country/Territory	United States
City	San Jose, CA
Period	9/19/10 → 9/22/10

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10.1109/CICC.2010.5617599

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Oh, T & Harjani, R 2010, A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os. in IEEE Custom Integrated Circuits Conference 2010, CICC 2010., 5617599, Proceedings of the Custom Integrated Circuits Conference, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, San Jose, CA, United States, 9/19/10. https://doi.org/10.1109/CICC.2010.5617599

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title = "A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os",

abstract = "We describe a multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture, particularly applicable to single-ended I/O. The MIMO architecture efficiently cancels crosstalk and improves jitter and eye-opening at the same time. A continuous-time prototype design was fabricated using a 130nm CMOS process and occupies 0.03mm2 of die area. The XTC equalizer performance has been verified for a variety of FR4 channel spacings and data rates. Measured eye diagrams show that the jitterpp reduces by 67%UI and the vertical eye opening increases by 58.2% at 5Gb/s. The prototype MIMO-XTC circuit consumes 2.8 mW/Gbps/lane which is roughly 2 times lower than other XTC schemes.",

author = "Taehyoun Oh and Ramesh Harjani",

year = "2010",

doi = "10.1109/CICC.2010.5617599",

language = "English (US)",

isbn = "9781424457588",

series = "Proceedings of the Custom Integrated Circuits Conference",

booktitle = "IEEE Custom Integrated Circuits Conference 2010, CICC 2010",

note = "32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 ; Conference date: 19-09-2010 Through 22-09-2010",

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AU - Oh, Taehyoun

AU - Harjani, Ramesh

PY - 2010

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N2 - We describe a multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture, particularly applicable to single-ended I/O. The MIMO architecture efficiently cancels crosstalk and improves jitter and eye-opening at the same time. A continuous-time prototype design was fabricated using a 130nm CMOS process and occupies 0.03mm2 of die area. The XTC equalizer performance has been verified for a variety of FR4 channel spacings and data rates. Measured eye diagrams show that the jitterpp reduces by 67%UI and the vertical eye opening increases by 58.2% at 5Gb/s. The prototype MIMO-XTC circuit consumes 2.8 mW/Gbps/lane which is roughly 2 times lower than other XTC schemes.

AB - We describe a multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture, particularly applicable to single-ended I/O. The MIMO architecture efficiently cancels crosstalk and improves jitter and eye-opening at the same time. A continuous-time prototype design was fabricated using a 130nm CMOS process and occupies 0.03mm2 of die area. The XTC equalizer performance has been verified for a variety of FR4 channel spacings and data rates. Measured eye diagrams show that the jitterpp reduces by 67%UI and the vertical eye opening increases by 58.2% at 5Gb/s. The prototype MIMO-XTC circuit consumes 2.8 mW/Gbps/lane which is roughly 2 times lower than other XTC schemes.

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A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os

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