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A 54 Mbps (3,6)-regular FPGA LDPC decoder
Tong Zhang,
K. K. Parhi
Electrical and Computer Engineering
Research output
:
Chapter in Book/Report/Conference proceeding
›
Chapter
87
Scopus citations
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Keyphrases
LDPC Decoder
100%
Regular LDPC
100%
Decoder
50%
Design Methodology
50%
Architecture-centric
50%
FPGA Device
50%
Rate 1
50%
AWGN Channel
50%
Decoder Design
50%
Bit Rate
50%
Xilinx FPGA
50%
Parallel Decoder Architecture
50%
Block Decoding
50%
Parallel Decoder
50%
Joint Codes
50%
Code Block
50%
Joint Encoders
50%
Code Design
50%
K-regular
50%
Engineering
Field Programmable Gate Arrays
100%
Joints (Structural Components)
50%
Bit Rate
50%
Code Block
50%
Computer Science
Field Programmable Gate Arrays
100%