Abstract
Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on an Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10-6 at 2 dB over an AWGN channel.
Original language | English (US) |
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Title of host publication | IEEE Workshop on Signal Processing Systems, SiPS |
Subtitle of host publication | Design and Implementation |
Pages | 127-132 |
Number of pages | 6 |
ISBN (Electronic) | 0780375874 |
DOIs | |
State | Published - 2002 |
Keywords
- AWGN channels
- Application specific integrated circuits
- Bit error rate
- Design methodology
- Field programmable gate arrays
- Hardware
- Iterative decoding
- Parity check codes
- Routing
- Throughput