A 54 Mbps (3,6)-regular FPGA LDPC decoder

Tong Zhang, K. K. Parhi

Research output: Chapter in Book/Report/Conference proceedingChapter

87 Scopus citations


Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3,6)-regular LDPC code decoder is implemented on an Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10-6 at 2 dB over an AWGN channel.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS
Subtitle of host publicationDesign and Implementation
Number of pages6
ISBN (Electronic)0780375874
StatePublished - 2002


  • AWGN channels
  • Application specific integrated circuits
  • Bit error rate
  • Design methodology
  • Field programmable gate arrays
  • Hardware
  • Iterative decoding
  • Parity check codes
  • Routing
  • Throughput


Dive into the research topics of 'A 54 Mbps (3,6)-regular FPGA LDPC decoder'. Together they form a unique fingerprint.

Cite this