A 5 Gbps 0.13 μm CMOS pilot-based clock and data recovery scheme for high-speed links

Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

This paper presents a pilot-based clock and data recovery (CDR) technique for high-speed serial link applications where a low-amplitude clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection-locked oscillator and is used to drive the receiver front-end samplers. The performance of the CDR technique is demonstrated using a 5 Gbps differential receiver fabricated in a 0.13 μm IBM CMOS technology. The clock and data recovery circuit implementation has an area of 0.171 mm2 and consumes 11.75 mA from a 1.5 V supply voltage at 5 Gbps. The recovered clock peak-to-peak and rms jitter at 5 Gbps are less than 10 ps (5%UI) and 1.6 ps (0.8%UI), respectively with an effective CDR loop bandwidth of approximately 28 MHz at a bit-error rate (BER) of 10-12. The proposed technique simplifies the CDR design and provides data and inter-symbol interference (ISI) independent performance with a small ≈5% pilot voltage overhead to the transmitted data signal.

Original languageEnglish (US)
Article number5518503
Pages (from-to)1533-1541
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume45
Issue number8
DOIs
StatePublished - Aug 1 2010

Keywords

  • Analog multi-tone
  • CML D-flip-flop
  • LC-VCO
  • NRZ
  • PAM2
  • data notch
  • decision feedback equalizer (DFE)
  • high-Q bandpass filter
  • injection locked oscillator (ILO)
  • inter-symbol interference (ISI)
  • mixer-based PLL
  • partial response
  • pilot-based CDR
  • plesiosynchronous
  • timing calibration

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