A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking

Kok Hin Teng; Tong Wu; Zhi Yang; Chun Huat Heng; Xiayun Liu

doi:10.1109/ASSCC.2015.7387454

A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking

Kok Hin Teng
, Tong Wu
, Zhi Yang
, Chun Huat Heng
, Xiayun Liu

Biomedical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK TX at MICS band is incorporated to support different data rate requirement. By using Exponential Component-Polynomial Component (EC-PC) spike processing unit with incremental principal component analysis (IPCA) engine, an overall 625× data reduction is achieved. The EC-PC unit is capable of detecting neural spikes of poor SNR. In TX, dual channels at 401 MHz and 403.8 MHz are supported by applying fixed injection and sequential injection locked techniques while attaining phase noise of -102 dBc/Hz@100 kHz offset. The measured EVM of 4.60%/9.55% with PA output power of -15dBm is achieved for QPSK@8 Mbps and [email protected] kbps. Fabricated in 65 nm CMOS with an area occupation of 1 mm², the design consumes a total current of 5~5.6 mA with maximum energy efficiency of 0.7 nJ/b.

Original language	English (US)
Title of host publication	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467371919
DOIs	https://doi.org/10.1109/ASSCC.2015.7387454
State	Published - Jan 19 2016
Event	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China Duration: Nov 9 2015 → Nov 11 2015

Publication series

Name	2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference	11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
Country/Territory	China
City	Xiamen, Fujian
Period	11/9/15 → 11/11/15

Bibliographical note

Funding Information:
This work is funded by National Research Foundation of Singapore (NRF) grant NRF-CRP-8-2011-01. We thank MediaTek Inc. (Singapore) for chip fabrication. The authors would also like to thank Dr. Wenfeng Zhao and Dr. Lei Wang for digital synthesis and chip layout assistance.

Publisher Copyright:
© 2015 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

EC-PC
injection locking
neural signal processing
reconfigurable
transmitter

Publisher link

10.1109/ASSCC.2015.7387454

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Teng, K. H., Wu, T., Yang, Z., Heng, C. H., & Liu, X. (2016). A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings Article 7387454 (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2015.7387454

A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking. / Teng, Kok Hin; Wu, Tong; Yang, Zhi et al.
2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. 7387454 (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Teng, KH, Wu, T, Yang, Z, Heng, CH & Liu, X 2016, A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking. in 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings., 7387454, 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xiamen, Fujian, China, 11/9/15. https://doi.org/10.1109/ASSCC.2015.7387454

Teng KH, Wu T, Yang Z, Heng CH, Liu X. A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking. In 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2016. 7387454. (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings). doi: 10.1109/ASSCC.2015.7387454

Teng, Kok Hin ; Wu, Tong ; Yang, Zhi et al. / A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking. 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2016. (2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings).

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abstract = "An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK TX at MICS band is incorporated to support different data rate requirement. By using Exponential Component-Polynomial Component (EC-PC) spike processing unit with incremental principal component analysis (IPCA) engine, an overall 625{\texttimes} data reduction is achieved. The EC-PC unit is capable of detecting neural spikes of poor SNR. In TX, dual channels at 401 MHz and 403.8 MHz are supported by applying fixed injection and sequential injection locked techniques while attaining phase noise of -102 dBc/Hz@100 kHz offset. The measured EVM of 4.60\%/9.55\% with PA output power of -15dBm is achieved for QPSK@8 Mbps and [email protected] kbps. Fabricated in 65 nm CMOS with an area occupation of 1 mm2, the design consumes a total current of 5\textasciitilde{}5.6 mA with maximum energy efficiency of 0.7 nJ/b.",

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N1 - Funding Information: This work is funded by National Research Foundation of Singapore (NRF) grant NRF-CRP-8-2011-01. We thank MediaTek Inc. (Singapore) for chip fabrication. The authors would also like to thank Dr. Wenfeng Zhao and Dr. Lei Wang for digital synthesis and chip layout assistance. Publisher Copyright: © 2015 IEEE.

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N2 - An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK TX at MICS band is incorporated to support different data rate requirement. By using Exponential Component-Polynomial Component (EC-PC) spike processing unit with incremental principal component analysis (IPCA) engine, an overall 625× data reduction is achieved. The EC-PC unit is capable of detecting neural spikes of poor SNR. In TX, dual channels at 401 MHz and 403.8 MHz are supported by applying fixed injection and sequential injection locked techniques while attaining phase noise of -102 dBc/Hz@100 kHz offset. The measured EVM of 4.60%/9.55% with PA output power of -15dBm is achieved for QPSK@8 Mbps and [email protected] kbps. Fabricated in 65 nm CMOS with an area occupation of 1 mm2, the design consumes a total current of 5~5.6 mA with maximum energy efficiency of 0.7 nJ/b.

AB - An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK TX at MICS band is incorporated to support different data rate requirement. By using Exponential Component-Polynomial Component (EC-PC) spike processing unit with incremental principal component analysis (IPCA) engine, an overall 625× data reduction is achieved. The EC-PC unit is capable of detecting neural spikes of poor SNR. In TX, dual channels at 401 MHz and 403.8 MHz are supported by applying fixed injection and sequential injection locked techniques while attaining phase noise of -102 dBc/Hz@100 kHz offset. The measured EVM of 4.60%/9.55% with PA output power of -15dBm is achieved for QPSK@8 Mbps and [email protected] kbps. Fabricated in 65 nm CMOS with an area occupation of 1 mm2, the design consumes a total current of 5~5.6 mA with maximum energy efficiency of 0.7 nJ/b.

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KW - injection locking

KW - neural signal processing

KW - reconfigurable

KW - transmitter

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A 400-MHz wireless neural signal processing IC with 625× on-chip data reduction and reconfigurable BFSK/QPSK transmitter based on sequential injection locking

Abstract

Publication series

Conference

Bibliographical note

UN SDGs

Keywords

Publisher link

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