An 8-channel wireless neural signal processing IC, which can perform real-time spike detection, alignment, feature extraction, and wireless data transmission is proposed. A reconfigurable BFSK/QPSK TX at MICS band is incorporated to support different data rate requirement. By using Exponential Component-Polynomial Component (EC-PC) spike processing unit with incremental principal component analysis (IPCA) engine, an overall 625× data reduction is achieved. The EC-PC unit is capable of detecting neural spikes of poor SNR. In TX, dual channels at 401 MHz and 403.8 MHz are supported by applying fixed injection and sequential injection locked techniques while attaining phase noise of -102 dBc/Hz@100 kHz offset. The measured EVM of 4.60%/9.55% with PA output power of -15dBm is achieved for QPSK@8 Mbps and BFSK@12.5 kbps. Fabricated in 65 nm CMOS with an area occupation of 1 mm2, the design consumes a total current of 5~5.6 mA with maximum energy efficiency of 0.7 nJ/b.
|Original language||English (US)|
|Title of host publication||2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Jan 19 2016|
|Event||11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China|
Duration: Nov 9 2015 → Nov 11 2015
|Name||2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings|
|Conference||11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015|
|Period||11/9/15 → 11/11/15|
Bibliographical noteFunding Information:
This work is funded by National Research Foundation of Singapore (NRF) grant NRF-CRP-8-2011-01. We thank MediaTek Inc. (Singapore) for chip fabrication. The authors would also like to thank Dr. Wenfeng Zhao and Dr. Lei Wang for digital synthesis and chip layout assistance.
© 2015 IEEE.
- injection locking
- neural signal processing