A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

M. Kim; M. Liu; L. Everson; G. Park; Y. Jeon; S. Kim; S. Lee; S. Song; C. H. Kim

doi:10.1109/IEDM19573.2019.8993574

A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

M. Kim
, M. Liu
, L. Everson
, G. Park
, Y. Jeon
, S. Kim
, S. Lee
, S. Song
, C. H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Scopus citations

Abstract

A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash array was demonstrated in a standard 65nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6μA. Positive and negative weights are stored in eFlash cells in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5% handwritten digit recognition accuracy which is close to the software accuracy of 99.0% for the same precision. This work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.

Original language	English (US)
Title of host publication	2019 IEEE International Electron Devices Meeting, IEDM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728140315
DOIs	https://doi.org/10.1109/IEDM19573.2019.8993574
State	Published - Dec 2019
Event	65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: Dec 7 2019 → Dec 11 2019

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2019-December
ISSN (Print)	0163-1918

Conference

Conference	65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country/Territory	United States
City	San Francisco
Period	12/7/19 → 12/11/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Publisher link

10.1109/IEDM19573.2019.8993574

Find It

Find It at U of M Libraries

Cite this

Kim, M., Liu, M., Everson, L., Park, G., Jeon, Y., Kim, S., Lee, S., Song, S., & Kim, C. H. (2019). A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process. In 2019 IEEE International Electron Devices Meeting, IEDM 2019 Article 8993574 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19573.2019.8993574

A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process. / Kim, M.; Liu, M.; Everson, L. et al.
2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993574 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kim, M, Liu, M, Everson, L, Park, G, Jeon, Y, Kim, S, Lee, S, Song, S & Kim, CH 2019, A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993574, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 12/7/19. https://doi.org/10.1109/IEDM19573.2019.8993574

Kim M, Liu M, Everson L, Park G, Jeon Y, Kim S et al. A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process. In 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8993574. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM19573.2019.8993574

@inproceedings{29a5050952b3403f90cfd186639ccd8a,

title = "A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process",

abstract = "A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash array was demonstrated in a standard 65nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6μA. Positive and negative weights are stored in eFlash cells in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5\% handwritten digit recognition accuracy which is close to the software accuracy of 99.0\% for the same precision. This work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.",

author = "M. Kim and M. Liu and L. Everson and G. Park and Y. Jeon and S. Kim and S. Lee and S. Song and Kim, \{C. H.\}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 65th Annual IEEE International Electron Devices Meeting, IEDM 2019 ; Conference date: 07-12-2019 Through 11-12-2019",

year = "2019",

month = dec,

doi = "10.1109/IEDM19573.2019.8993574",

language = "English (US)",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",

}

TY - GEN

T1 - A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

AU - Kim, M.

AU - Liu, M.

AU - Everson, L.

AU - Park, G.

AU - Jeon, Y.

AU - Kim, S.

AU - Lee, S.

AU - Song, S.

AU - Kim, C. H.

PY - 2019/12

Y1 - 2019/12

N2 - A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash array was demonstrated in a standard 65nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6μA. Positive and negative weights are stored in eFlash cells in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5% handwritten digit recognition accuracy which is close to the software accuracy of 99.0% for the same precision. This work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.

AB - A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash array was demonstrated in a standard 65nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6μA. Positive and negative weights are stored in eFlash cells in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5% handwritten digit recognition accuracy which is close to the software accuracy of 99.0% for the same precision. This work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.

UR - https://www.scopus.com/pages/publications/85081049528

UR - https://www.scopus.com/pages/publications/85081049528#tab=citedBy

U2 - 10.1109/IEDM19573.2019.8993574

DO - 10.1109/IEDM19573.2019.8993574

M3 - Conference contribution

AN - SCOPUS:85081049528

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 65th Annual IEEE International Electron Devices Meeting, IEDM 2019

Y2 - 7 December 2019 through 11 December 2019

ER -

A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

Abstract

Publication series

Conference

Bibliographical note

Publisher link

Find It

Other files and links

Fingerprint

Cite this