A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash array was demonstrated in a standard 65nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6μA. Positive and negative weights are stored in eFlash cells in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5% handwritten digit recognition accuracy which is close to the software accuracy of 99.0% for the same precision. This work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.
|Original language||English (US)|
|Title of host publication||2019 IEEE International Electron Devices Meeting, IEDM 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|State||Published - Dec 2019|
|Event||65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States|
Duration: Dec 7 2019 → Dec 11 2019
|Name||Technical Digest - International Electron Devices Meeting, IEDM|
|Conference||65th Annual IEEE International Electron Devices Meeting, IEDM 2019|
|Period||12/7/19 → 12/11/19|
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