A 3D miniaturization method for low impedance designs

S. Riki Banerjee, Rhonda Franklin Drayton

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Microstrip interconnects with a V conductor are designed, fabricated, and measured to provide a compact solution for designs requiring low characteristic impedance lines. S-parameter curves are shown up to 35 GHz for 0.5 cm long designs. The 308 μm deep V structure produces a 33.8 Ω line with strong standing waves and reflections under 5 dB. To further reduce the impedance, a partial shield is added that results in 6.7 times reduction of signal line width, near elimination of open end effect, and excellent correlation with a standard 15 Ω microstrip up to 25 GHz. A filter demonstration shows near ideal behavior in 3 dB response and low return loss when compared to a similar design.

Original languageEnglish (US)
Title of host publicationProceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005
Pages71-74
Number of pages4
DOIs
StatePublished - Dec 1 2005
Event9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005 - Garmisch-Partenkirchen, Germany
Duration: May 10 2005May 13 2005

Publication series

NameProceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005
Volume2005

Other

Other9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005
CountryGermany
CityGarmisch-Partenkirchen
Period5/10/055/13/05

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Banerjee, S. R., & Drayton, R. F. (2005). A 3D miniaturization method for low impedance designs. In Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005 (pp. 71-74). [1500902] (Proceedings - 9th IEEE Workshop on Signal Propagation on Interconnects, SPI 2005; Vol. 2005). https://doi.org/10.1109/SPI.2005.1500902