A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI

Pulkit Jain, Ayan Paul, Xiaofei Wang, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A scalable test structure for recovery free evaluation of the impact of NBTI and PBTI on read/write operation in a SRAM macro has been developed. A novel non-invasive methodology keeps the stress interrupts for measurements within a few microseconds, preventing unwanted BTI recovery, while providing a parallel stress-measure capability on 32kb sub-arrays. Measurement results in a 32nm high-κ/metal-gate silicon-on-insulator process show that proposed schemes provides 35mV better accuracy in read VMIN and 10X accuracy in BFR.

Original languageEnglish (US)
Title of host publication2012 IEEE International Electron Devices Meeting, IEDM 2012
DOIs
StatePublished - Dec 1 2012
Event2012 IEEE International Electron Devices Meeting, IEDM 2012 - San Francisco, CA, United States
Duration: Dec 10 2012Dec 13 2012

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Other

Other2012 IEEE International Electron Devices Meeting, IEDM 2012
CountryUnited States
CitySan Francisco, CA
Period12/10/1212/13/12

    Fingerprint

Cite this

Jain, P., Paul, A., Wang, X., & Kim, C. H. (2012). A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI. In 2012 IEEE International Electron Devices Meeting, IEDM 2012 [6479014] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2012.6479014