@inproceedings{7c8481b8f3f4450cbb4090996cceafb1,
title = "A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter",
abstract = "An adaptive PLL implemented in a 0.9V 32nm process achieves optimal clock data compensation across a wide range of PVT and operating conditions. This is accomplished by an automated supply-noise sensitivity tracking loop which constantly monitors the BER of a tunable critical path circuit. The proposed PLL achieves a 14.5% to 15.6% improvement in processor Fmax over a conventional design for a 90mV supply noise and has a 92.1% smaller area by employing ultra-high density deep trench capacitors in the loop filter.",
author = "Bongjin Kim and Weichao Xu and Kim, {Chris H.}",
year = "2013",
month = sep,
day = "17",
language = "English (US)",
isbn = "9784863483484",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
booktitle = "2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers",
note = "2013 Symposium on VLSI Circuits, VLSIC 2013 ; Conference date: 12-06-2013 Through 14-06-2013",
}