A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter

Bongjin Kim, Weichao Xu, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

An adaptive PLL implemented in a 0.9V 32nm process achieves optimal clock data compensation across a wide range of PVT and operating conditions. This is accomplished by an automated supply-noise sensitivity tracking loop which constantly monitors the BER of a tunable critical path circuit. The proposed PLL achieves a 14.5% to 15.6% improvement in processor Fmax over a conventional design for a 90mV supply noise and has a 92.1% smaller area by employing ultra-high density deep trench capacitors in the loop filter.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
StatePublished - Sep 17 2013
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: Jun 12 2013Jun 14 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period6/12/136/14/13

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Kim, B., Xu, W., & Kim, C. H. (2013). A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers [6578648] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).