Abstract
A digital-intensive four-level pulse amplitude (PAM-4) transceiver featuring a 2-tap time-based decision feedback equalization (TB-DFE) circuit was demonstrated in a 65 nm GP CMOS process. A novel inverter-based differential voltage-to-time converter (DVTC) increases the linearity and dynamic range compared to a prior time-based DFE approach enabling reliable PAM-4 operation. The four-level signal comparison and DFE operation were performed entirely in the time domain using programmable delays and a phase detector (PD). Using an on-chip bit error rate (BER) monitor, we verified a BER less than 10-12 while achieving an energy-efficiency of 0.97pJ/b at a 32Gb/s data rate. The transmitter (TX) and receiver (RX) circuits occupy an area of 0.009 mm2.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 1943-1951 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
| Volume | 69 |
| Issue number | 5 |
| DOIs | |
| State | Published - May 1 2022 |
| Externally published | Yes |
Bibliographical note
Publisher Copyright:© 2004-2012 IEEE.
Keywords
- Delay lines
- Delays
- Digital-intensive
- Inverters
- Linearity
- Modulation
- Optical signal processing
- Transceivers
- differential voltage-to-time converter
- eye-diagram.
- in-situ channel loss monitor
- time-based decision feedback equalizer
- eye-diagram
