A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors

Po Wei Chiu, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

Abstract

A digital-intensive four-level pulse amplitude (PAM-4) transceiver featuring a 2-tap time-based decision feedback equalization (TB-DFE) circuit was demonstrated in a 65 nm GP CMOS process. A novel inverter-based differential voltage-to-time converter (DVTC) increases the linearity and dynamic range compared to a prior time-based DFE approach enabling reliable PAM-4 operation. The four-level signal comparison and DFE operation were performed entirely in the time domain using programmable delays and a phase detector (PD). Using an on-chip bit error rate (BER) monitor, we verified a BER less than 10-12 while achieving an energy-efficiency of 0.97pJ/b at a 32Gb/s data rate. The transmitter (TX) and receiver (RX) circuits occupy an area of 0.009 mm2.

Original languageEnglish (US)
Pages (from-to)1943-1951
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume69
Issue number5
DOIs
StatePublished - May 1 2022

Bibliographical note

Publisher Copyright:
© 2004-2012 IEEE.

Keywords

  • Delay lines
  • Delays
  • Digital-intensive
  • Inverters
  • Linearity
  • Modulation
  • Optical signal processing
  • Transceivers
  • differential voltage-to-time converter
  • eye-diagram.
  • in-situ channel loss monitor
  • time-based decision feedback equalizer
  • eye-diagram

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