A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power consumption; these include: Variable node initialization, bit-flipping post-processing and posterior-information-based hard decision. Moreover, a random number based probability stochastic sequences generator is proposed to reduce hardware resources. Chip test results from an LDPC decoder for the 10GBASE-T standard (2048, 1723) code using 65 nm CMOS process demonstrate a 74.3% reduction in average decoding cycles at 4.4 dB with satisfactory decoding performance. The decoder supports 65.38 Gb/s throughput at 420 MHz and requires 1.1W power consumption. Compared with other works, the proposed decoder can achieve lower power and average decoding cycles with similar error performance.
|Original language||English (US)|
|Title of host publication||Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - Nov 2019|
|Event||15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China|
Duration: Nov 4 2019 → Nov 6 2019
|Name||Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019|
|Conference||15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019|
|Period||11/4/19 → 11/6/19|
Bibliographical notePublisher Copyright:
© 2019 IEEE.
- Bit-Flipping algorithm
- High throughput decoder
- Stochastic computation