A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm

Qichen Zhang; Yun Chen; Xiaoyang Zeng; Keshab K. Parhi; Borivoje Nikolic

doi:10.1109/A-SSCC47793.2019.9056915

A 3.01 mm² 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm

Qichen Zhang, Yun Chen, Xiaoyang Zeng, Keshab K. Parhi, Borivoje Nikolic

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power consumption; these include: Variable node initialization, bit-flipping post-processing and posterior-information-based hard decision. Moreover, a random number based probability stochastic sequences generator is proposed to reduce hardware resources. Chip test results from an LDPC decoder for the 10GBASE-T standard (2048, 1723) code using 65 nm CMOS process demonstrate a 74.3% reduction in average decoding cycles at 4.4 dB with satisfactory decoding performance. The decoder supports 65.38 Gb/s throughput at 420 MHz and requires 1.1W power consumption. Compared with other works, the proposed decoder can achieve lower power and average decoding cycles with similar error performance.

Original language	English (US)
Title of host publication	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	271-274
Number of pages	4
ISBN (Electronic)	9781728151069
DOIs	https://doi.org/10.1109/A-SSCC47793.2019.9056915
State	Published - Nov 2019
Event	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China Duration: Nov 4 2019 → Nov 6 2019

Publication series

Name	Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference	15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/Territory	China
City	Macao
Period	11/4/19 → 11/6/19

Bibliographical note

Publisher Copyright:
© 2019 IEEE.

Keywords

Bit-Flipping algorithm
High throughput decoder
Stochastic computation

Publisher link

10.1109/A-SSCC47793.2019.9056915

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Cite this

Zhang, Q., Chen, Y., Zeng, X., Parhi, K. K., & Nikolic, B. (2019). A 3.01 mm² 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 (pp. 271-274). Article 9056915 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/A-SSCC47793.2019.9056915

A 3.01 mm² 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. / Zhang, Qichen; Chen, Yun; Zeng, Xiaoyang et al.
Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 271-274 9056915 (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, Q, Chen, Y, Zeng, X, Parhi, KK & Nikolic, B 2019, A 3.01 mm² 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. in Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019., 9056915, Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Institute of Electrical and Electronics Engineers Inc., pp. 271-274, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, Macao, China, 11/4/19. https://doi.org/10.1109/A-SSCC47793.2019.9056915

Zhang Q, Chen Y, Zeng X, Parhi KK, Nikolic B. A 3.01 mm² 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. In Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 271-274. 9056915. (Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019). doi: 10.1109/A-SSCC47793.2019.9056915

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abstract = "A fully-parallel high-throughput LDPC decoder architecture leads to high power consumption and large area. Using stochastic logic, this paper proposes three novel strategies to improve throughput and reduce power consumption; these include: Variable node initialization, bit-flipping post-processing and posterior-information-based hard decision. Moreover, a random number based probability stochastic sequences generator is proposed to reduce hardware resources. Chip test results from an LDPC decoder for the 10GBASE-T standard (2048, 1723) code using 65 nm CMOS process demonstrate a 74.3% reduction in average decoding cycles at 4.4 dB with satisfactory decoding performance. The decoder supports 65.38 Gb/s throughput at 420 MHz and requires 1.1W power consumption. Compared with other works, the proposed decoder can achieve lower power and average decoding cycles with similar error performance.",

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