TY - JOUR
T1 - A 3 × 5-Gb/s multilane low-power 0.18-μ m CMOS pseudorandom bit sequence generator
AU - Sham, Kin Joe
AU - Bommalingaiahnapallya, Shubha
AU - Ahmadi, Mahmoud Reza
AU - Harjani, Ramesh
PY - 2008/5
Y1 - 2008/5
N2 - A low-power, three-lane, 231- 1 pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-μm CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the fT of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.
AB - A low-power, three-lane, 231- 1 pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-μm CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the fT of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.
KW - Active inductor
KW - Crosstalk
KW - High-speed serial links
KW - Pseudorandom bit sequence (PRBS) generator
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U2 - 10.1109/TCSII.2007.912696
DO - 10.1109/TCSII.2007.912696
M3 - Article
AN - SCOPUS:44849144045
SN - 1549-7747
VL - 55
SP - 432
EP - 436
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 5
ER -