A 3 × 5-Gb/s multilane low-power 0.18-μ m CMOS pseudorandom bit sequence generator

Kin Joe Sham, Shubha Bommalingaiahnapallya, Mahmoud Reza Ahmadi, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

16 Scopus citations


A low-power, three-lane, 231- 1 pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-μm CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the fT of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.

Original languageEnglish (US)
Pages (from-to)432-436
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number5
StatePublished - May 2008


  • Active inductor
  • Crosstalk
  • High-speed serial links
  • Pseudorandom bit sequence (PRBS) generator


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