Abstract
A truly logic-compatible gain cell eDRAM macro with no boosted supplies is presented. A 2T1C gain cell implemented only with regular thin oxide devices consists of an asymmetric 2T cell and a coupling PMOS capacitor. The PMOS capacitor ensures proper operation even without a boosted supply by utilizing a beneficial coupling for read and a preferential boosting for write. A repair scheme based on a single-ended 7T SRAM has features such as a local differential write and shared control with the main 2T1C array. A storage voltage monitor is proposed to track the retention characteristics of a gain cell eDRAM under PVT variations and to adjust its refresh rate adaptively. A 128 kb eDRAM test chip implemented in a 65 nm Low-Power (LP) process operates at a random access frequency of 714 MHz with a static power dissipation of 161.8 μW per Mb for a 500 μs refresh rate at 1.1 V and 85°C.
Original language | English (US) |
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Article number | 6320714 |
Pages (from-to) | 2517-2526 |
Number of pages | 10 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 47 |
Issue number | 10 |
DOIs | |
State | Published - Oct 17 2012 |
Keywords
- 2T
- 2T1C gain cell
- 7T SRAM
- cache
- embedded memory
- logic-compatible eDRAM
- repair scheme
- retention time
- storage monitor
- temperature sensor