A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

J. O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, Ramesh Harjani, S. Reynolds, J. A. Tierno, D. Friedman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012
DOIs
StatePublished - Nov 26 2012
Event34th Annual Custom Integrated Circuits Conference, CICC 2012 - San Jose, CA, United States
Duration: Sep 9 2012Sep 12 2012

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other34th Annual Custom Integrated Circuits Conference, CICC 2012
CountryUnited States
CitySan Jose, CA
Period9/9/129/12/12

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