@inproceedings{5eedfc5e717c47cca7464260a4320c58,
title = "A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS",
abstract = "A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.",
author = "Plouchart, {J. O.} and M. Ferriss and A. Natarajan and A. Valdes-Garcia and B. Sadhu and A. Rylyakov and B. Parker and M. Beakes and A. Babakani and S. Yaldiz and L. Pileggi and Ramesh Harjani and S. Reynolds and Tierno, {J. A.} and D. Friedman",
year = "2012",
doi = "10.1109/CICC.2012.6330593",
language = "English (US)",
isbn = "9781467315555",
series = "Proceedings of the Custom Integrated Circuits Conference",
booktitle = "Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012",
note = "34th Annual Custom Integrated Circuits Conference, CICC 2012 ; Conference date: 09-09-2012 Through 12-09-2012",
}