A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS

Jean Olivier Plouchart, Mark A. Ferriss, Arun S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, Benjamin D. Parker, M. Beakes, Aydin Babakhani, Soner Yaldiz, Larry Pileggi, Ramesh Harjani, Scott Reynolds, Jose A. Tierno, Daniel Friedman

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

Original languageEnglish (US)
Article number6541965
Pages (from-to)2009-2017
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number8
DOIs
StatePublished - Jun 25 2013

Keywords

  • Millimeter wave integrated circuits
  • phase locked loops
  • phase noise
  • silicon-on-insulator

Fingerprint Dive into the research topics of 'A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS'. Together they form a unique fingerprint.

Cite this