A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer

Po Wei Chiu; Muqing Liu; Qianying Tang; Chris H. Kim

doi:10.1109/ASSCC.2018.8579267

A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer

Po Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

An 8 Gb/s time-to-digital converter (TDC) based receiver with a time-based front-end in 65nm CMOS is specifically designed for in-package serial link applications. The proposed receiver converts the channel signal to a corresponding time delay which is amplified by a novel delay line based time amplifier. Next, a time-to-digital converter generates a 4-bit code which is used for digital equalization. The proposed design is digital intensive and hence highly resilient to voltage headroom and/or PVT issues. A bathtub curve and time domain eye-diagram were measured by an in-situ bit-error-rate (BER) monitor circuit. An energy-efficiency of 2.1 pJ/b was achieved at 8 Gb/s for a 7 mm link. The receiver area is 240×120μm ² .

Original language	English (US)
Title of host publication	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	187-190
Number of pages	4
ISBN (Electronic)	9781538664124
DOIs	https://doi.org/10.1109/ASSCC.2018.8579267
State	Published - Dec 14 2018
Event	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan, Province of China Duration: Nov 5 2018 → Nov 7 2018

Publication series

Name	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Other

Other	2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Country/Territory	Taiwan, Province of China
City	Tainan
Period	11/5/18 → 11/7/18

Bibliographical note

Publisher Copyright:
© 2018 IEEE.

Keywords

Time-based
digital equalization
digital intensive
inverter-based
system-in-package (SiP)
time-to-digital converter (TDC)

Publisher link

10.1109/ASSCC.2018.8579267

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Chiu, P. W., Liu, M., Tang, Q., & Kim, C. H. (2018). A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings (pp. 187-190). Article 8579267 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2018.8579267

A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. / Chiu, Po Wei; Liu, Muqing; Tang, Qianying et al.
2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 187-190 8579267 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chiu, PW, Liu, M, Tang, Q & Kim, CH 2018, A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. in 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings., 8579267, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 187-190, 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, Province of China, 11/5/18. https://doi.org/10.1109/ASSCC.2018.8579267

Chiu PW, Liu M, Tang Q, Kim CH. A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. In 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 187-190. 8579267. (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings). doi: 10.1109/ASSCC.2018.8579267

Chiu, Po Wei ; Liu, Muqing ; Tang, Qianying et al. / A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 187-190 (2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings).

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abstract = " An 8 Gb/s time-to-digital converter (TDC) based receiver with a time-based front-end in 65nm CMOS is specifically designed for in-package serial link applications. The proposed receiver converts the channel signal to a corresponding time delay which is amplified by a novel delay line based time amplifier. Next, a time-to-digital converter generates a 4-bit code which is used for digital equalization. The proposed design is digital intensive and hence highly resilient to voltage headroom and/or PVT issues. A bathtub curve and time domain eye-diagram were measured by an in-situ bit-error-rate (BER) monitor circuit. An energy-efficiency of 2.1 pJ/b was achieved at 8 Gb/s for a 7 mm link. The receiver area is 240×120μm 2 .",

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A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer

Abstract

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Keywords

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