A 20 GS/s 1.2 v 0.13 μm CMOS switched cascode track-and-hold amplifier

Heather Orser, Anand Gopinath

Research output: Contribution to journalArticlepeer-review

27 Scopus citations

Abstract

A low voltage, low power, high sampling rate trackand-hold amplifier (THA) architecture is proposed. The THA samples at 20 GS/s and combines a distributed amplifier and a switched cascode stage. Power consumption for the circuit is 71 mW and it occupies 0.09 mm2 in 0.13 μm CMOS. The THA delivers up to 34 dB spur-free dynamic range (SFDR) and - 32 dB total harmonic distortion (THD) at a supply voltage of 1.2 V. Input return loss remains below - 10 dB over all frequencies of interest, while output return loss remains below - 15 dB.

Original languageEnglish (US)
Article number5475210
Pages (from-to)512-516
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number7
DOIs
StatePublished - Jul 2010

Bibliographical note

Funding Information:
Manuscript received November 17, 2009; revised January 27, 2010; accepted March 19, 2010. Date of publication June 1, 2010; date of current version July 16, 2010. This work was supported in part by the fabrication provided by UMC. This paper was recommended by Associate Editor S. Pennisi. H. Orser is with Medtronic Incorporated, Minneapolis, MN 55432 USA (e-mail: orse0008@umn.edu). A. Gopinath is with the University of Minnesota, Minneapolis, MN 55455 USA (e-mail: gopinath@umn.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2010.2048484

Copyright:
Copyright 2010 Elsevier B.V., All rights reserved.

Keywords

  • High-speed integrated circuits
  • sample-and-hold amplifiers (SHAs)
  • sampled data circuits
  • track-and-hold amplifiers (THAs)

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