A 1mW 4b 1GS/s delay-line based analog-to-digital converter

Keyphrases

• Analog-to-digital Converter 100%
• Delay-line-based 100%
• CMOS Technology 50%
• Proposed Architecture 50%
• Power Consumption 50%
• Conversion Method 50%
• CMOS Scaling 50%
• New Architecture 50%
• Novel Analogues 50%
• Variable Delay Line 50%
• High-speed Applications 50%
• Digital Implementation 50%
• 65nm CMOS 50%
• Voltage Conversion 50%
• Quantization Method 50%
• ADC Performance 50%
• Digital Architecture 50%
• Analogue-digital 50%
• Digital CMOS 50%

Computer Science

• Power Consumption 100%
• Analog-to-Digital Converter 100%
• Enhance Performance 100%

Engineering

• Electric Delay Lines 100%
• Analog-to-Digital Converter 100%
• Electric Power Utilization 33%
• Speed Application 33%