A 1mW 4b 1GS/s delay-line based analog-to-digital converter

Yahya M. Tousi, Guansheng Li, Arjang Hassibi, Ehsan Afshari

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.

Original languageEnglish (US)
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1121-1124
Number of pages4
DOIs
StatePublished - Oct 26 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China
Duration: May 24 2009May 27 2009

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan, Province of China
CityTaipei
Period5/24/095/27/09

Fingerprint Dive into the research topics of 'A 1mW 4b 1GS/s delay-line based analog-to-digital converter'. Together they form a unique fingerprint.

Cite this