A 1mW 4b 1GS/s delay-line based analog-to-digital converter

Yahya M. Tousi; Guansheng Li; Arjang Hassibi; Ehsan Afshari

doi:10.1109/ISCAS.2009.5117957

A 1mW 4b 1GS/s delay-line based analog-to-digital converter

Yahya M. Tousi, Guansheng Li, Arjang Hassibi, Ehsan Afshari

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.

Original language	English (US)
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	1121-1124
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5117957
State	Published - 2009
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China Duration: May 24 2009 → May 27 2009

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan, Province of China
City	Taipei
Period	5/24/09 → 5/27/09

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10.1109/ISCAS.2009.5117957

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A 1mW 4b 1GS/s delay-line based analog-to-digital converter. / Tousi, Yahya M.; Li, Guansheng; Hassibi, Arjang et al.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 1121-1124 5117957 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tousi, YM, Li, G, Hassibi, A & Afshari, E 2009, A 1mW 4b 1GS/s delay-line based analog-to-digital converter. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5117957, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1121-1124, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, Province of China, 5/24/09. https://doi.org/10.1109/ISCAS.2009.5117957

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abstract = "In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.",

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AB - In this paper we introduce a novel Analog-to-Digital architecture for high speed applications that is compatible with digital CMOS and surpasses the issues with traditional voltage conversion techniques. The quantization method is based on the delay-to-digital concept as a means to quantize a variable delay line. A 4bit 1GS/s ADC with 1mW power consumption is designed in 65nm CMOS based on the proposed architecture. The new architecture is highly scalable with CMOS technology and because of its delay-line-based core, the ADCs performance enhances with further CMOS scaling and provides a promising method for the trend toward more digital implementation of circuits.

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A 1mW 4b 1GS/s delay-line based analog-to-digital converter

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