A +18dBm IIP3 LNA in 0.35μm CMOS

Y. Ding, R. Harjani

Research output: Contribution to journalConference articlepeer-review

86 Scopus citations

Abstract

A technique for improving linearity in low noise amplifiers (LNA) designs without any change in power, noise and gain performances was proposed. The measured performance for IIP3 LNA for the design was +18dBm. The use of MOSFET- based LNA's was suggested to meet the high IIP3 requirements and power consumption with low-voltage processes. A two-tone method was used to measure IIP3. Experimental results showed IIP3 without harmonic cancellation was +5dBm and IIP3 with harmonic cancellation was +18dBm.

Original languageEnglish (US)
Pages (from-to)162-163+443
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
StatePublished - Jan 1 2001
EventDigest of Technical Papers - IEEE International Solid-State Circuits Conference -
Duration: Feb 5 2001Feb 6 2001

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