The impact of Electromigration (EM) on the Bit-Error-Rate (BER) of signal interconnect paths was experimentally examined. An array-based test-vehicle for tracking Bit-Error-Rate (BER) degradation of signal interconnects subject to Direct-Current (DC) EM stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. The proposed test structure features a ring-based Voltage-Controlled-Oscillator (VCO), a bit-pattern generator and local BER sampling monitors which enable bitwise tracking of '0' and '1' errors separately, further simplifying the overall test-setup and allowing for high precision characterization of EM induced resistance shifts using only digital circuits. Measurement data collected from the 16nm prototype reveals unique insights into EM induced signal path degradation that was not available prior to this work. Our experimental studies suggest that monitoring the BER of an interconnect path could be used as a new metric for capturing EM induced resistance shifts in a real system, in lieu of the conventional approach which focuses on monitoring standalone wire resistances. Supplemental simulations showcasing the projected degradation in the interconnect path operating frequency as a function of stress time constructed from resistance traces sampled from identical wires implemented in the same process reaffirm the measurement trends.
|Original language||English (US)|
|Number of pages||11|
|Journal||IEEE Transactions on Device and Materials Reliability|
|State||Published - Jun 1 2022|
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