A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition

Tong Wu, Jian Xu, Yong Lian, Azam Khalili, Amir Rastegarnia, Cuntai Guan, Zhi Yang

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm2 for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

Original languageEnglish (US)
Article number7055372
Pages (from-to)3-17
Number of pages15
JournalIEEE Transactions on Biomedical Circuits and Systems
Volume10
Issue number1
DOIs
StatePublished - Feb 1 2016

Fingerprint

Application specific integrated circuits
Polynomials
Decomposition
Experiments
Closed loop systems
Information management
Integrated circuits
Decoding
Electric power utilization
Tuning
Detectors

Keywords

  • EC-PC regression
  • multichannel digital system
  • neural signal processing
  • unsupervised spike detection

Cite this

A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition. / Wu, Tong; Xu, Jian; Lian, Yong; Khalili, Azam; Rastegarnia, Amir; Guan, Cuntai; Yang, Zhi.

In: IEEE Transactions on Biomedical Circuits and Systems, Vol. 10, No. 1, 7055372, 01.02.2016, p. 3-17.

Research output: Contribution to journalArticle

Wu, Tong ; Xu, Jian ; Lian, Yong ; Khalili, Azam ; Rastegarnia, Amir ; Guan, Cuntai ; Yang, Zhi. / A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition. In: IEEE Transactions on Biomedical Circuits and Systems. 2016 ; Vol. 10, No. 1. pp. 3-17.
@article{7a913fd005304b3c9609bdec501636c3,
title = "A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition",
abstract = "In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm2 for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.",
keywords = "EC-PC regression, multichannel digital system, neural signal processing, unsupervised spike detection",
author = "Tong Wu and Jian Xu and Yong Lian and Azam Khalili and Amir Rastegarnia and Cuntai Guan and Zhi Yang",
year = "2016",
month = "2",
day = "1",
doi = "10.1109/TBCAS.2015.2389266",
language = "English (US)",
volume = "10",
pages = "3--17",
journal = "IEEE Transactions on Biomedical Circuits and Systems",
issn = "1932-4545",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "1",

}

TY - JOUR

T1 - A 16-Channel Nonparametric Spike Detection ASIC Based on EC-PC Decomposition

AU - Wu, Tong

AU - Xu, Jian

AU - Lian, Yong

AU - Khalili, Azam

AU - Rastegarnia, Amir

AU - Guan, Cuntai

AU - Yang, Zhi

PY - 2016/2/1

Y1 - 2016/2/1

N2 - In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm2 for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

AB - In extracellular neural recording experiments, detecting neural spikes is an important step for reliable information decoding. A successful implementation in integrated circuits can achieve substantial data volume reduction, potentially enabling a wireless operation and closed-loop system. In this paper, we report a 16-channel neural spike detection chip based on a customized spike detection method named as exponential component-polynomial component (EC-PC) algorithm. This algorithm features a reliable prediction of spikes by applying a probability threshold. The chip takes raw data as input and outputs three data streams simultaneously: field potentials, band-pass filtered neural data, and spiking probability maps. The algorithm parameters are on-chip configured automatically based on input data, which avoids manual parameter tuning. The chip has been tested with both in vivo experiments for functional verification and bench-top experiments for quantitative performance assessment. The system has a total power consumption of 1.36 mW and occupies an area of 6.71 mm2 for 16 channels. When tested on synthesized datasets with spikes and noise segments extracted from in vivo preparations and scaled according to required precisions, the chip outperforms other detectors. A credit card sized prototype board is developed to provide power and data management through a USB port.

KW - EC-PC regression

KW - multichannel digital system

KW - neural signal processing

KW - unsupervised spike detection

UR - http://www.scopus.com/inward/record.url?scp=84924560325&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84924560325&partnerID=8YFLogxK

U2 - 10.1109/TBCAS.2015.2389266

DO - 10.1109/TBCAS.2015.2389266

M3 - Article

C2 - 25769170

AN - SCOPUS:84924560325

VL - 10

SP - 3

EP - 17

JO - IEEE Transactions on Biomedical Circuits and Systems

JF - IEEE Transactions on Biomedical Circuits and Systems

SN - 1932-4545

IS - 1

M1 - 7055372

ER -