A 16-bit x 16-bit 1.2 p CMOS Multiplier with Low Latency Vector Merging

Keyphrases

• 16-bit 100%
• Low Latency 100%
• Radix-2 66%
• Signed Digit 66%
• Latency 33%
• VLSI Architecture 33%
• Supply Voltage 33%
• Clock Frequency 33%
• VLSI Implementation 33%
• Bit Level 33%
• Binary Forms 33%
• Multiplier Architecture 33%
• Fast Conversions 33%
• Clocking Scheme 33%
• Binary Adder 33%
• Pipelined multiplier 33%
• Edge Triggered 33%
• Array multiplier 33%
• Half Adder 33%
• Binary Array 33%
• Adder Cells 33%
• Positive Edge 33%

Computer Science

• radix 2 100%
• Pipelining 50%
• Conversion Scheme 50%
• Clocking Scheme 50%
• Very large-scale integration (VLSI) architecture 50%
• Clock Frequency 50%
• Triggered Register 50%
• Half Adder 50%